1. Field of the Invention
The present invention relates to a method for manufacturing a bipolar transistor.
2. Description of the Related Art
Recent demand for a high speed signal processing device has rapidly increased. To meet such a demand, a bipolar transistor for high speed signal processing has been developed. The bipolar transistor may reduce a base resistance by reducing a distance between a base region and an emitter region.
FIG. 1 is a cross-sectional view showing a construction of a high speed bipolar transistor according to the related art.
As shown in FIG. 1, a buried layer 110 is formed on a substrate 10, and a device isolation layer 140 is formed on the buried layer 110. Here, the device isolation layer 140 is divided into a first well 120a and a second well 120b. A first active region is formed at the first well 120a and a second active region is formed at the second well 120b. An emitter region 150b and a base region 152b are formed inside the first active region of the first well 120a. A collector region 156a is formed inside the second active region of the second well 120b. An emitter electrode 150a is formed at the emitter region 150 to be connected to the first contact plug 150c. A collector region 156a is connected to a second contact plug 156c. A base electrode 152a is formed at the base region 152b to be connected to a third contact plug 152c. A pad oxide layer 160 is formed between the base electrode 152a and the emitter electrode 150a. The first, second, and third contact plugs 150c, 156c, and 152c are connected to the emitter region 150b, the collector region 156a, and the base region 152b through the inter layer dielectric 170, respectively.
On the other hand, in the bipolar transistor formed as mentioned above, the pad oxide layer 160 isolates the emitter electrode 150a and the base electrode 152a. Ions doped in the emitter electrode 150a are diffused to form the emitter region 150b, and ions doped into the base electrode 152a are diffused to form the base region 152b. 
However, when forming the aforementioned bipolar transistor, a height of the interlayer dielectric 170 including the emitter electrode 150a and the base electrode 152a may be relatively great in order to secure a CMP process margin during formation of the contact plugs to the electrodes. As a result, it becomes difficult to more highly integrate a device.
Moreover, two polysilicon layer formation and etching processes are performed to form the emitter electrode 150a and the base electrode 152a, respectively. Thus, it may be difficult to simplify a process. During an etching process for forming the contact plugs, an overetching loss of the polysilicon layer constituting the electrodes can be incurred.